IS43TR16128B-15HBLI - 

SDRAM, DDR3, 2GB, 1333MT/S, FBGA-96


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Product Information

128M x 16bit
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MSL 3 - 168 hours
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Product Overview

The IS43TR16128B-15HBLI is a 128Mx16 DDR3 SDRAM with 1333MT/s data rate. For application flexibility, various functions, features and modes are programmable in four mode registers, provided by the DDR3 SDRAM, as user defined variables and they must be programmed via a Mode Register Set (MRS) command. As the default values of the Mode Registers (MR#) are not defined, contents of Mode Registers must be fully initialized and/or re-initialized, i.e. written, after power up and/or reset for proper operation. Also the contents of the Mode Registers can be altered by re-executing the MRS command during normal operation. When programming the mode registers, even if the user chooses to modify only a sub-set of the MRS fields, all address fields within the accessed mode register must be redefined when the MRS command is issued. MRS command and DLL Reset do not affect array contents, which means these commands can be executed any time after power-up without affecting the array contents.
  • VDD and VDDQ = 1.5V ±0.075V Standard Voltage
  • VDD and VDDQ = 1.35V + 0.1V, -0.067V low voltage (L), backward compatible to 1.5V
  • High speed data transfer rates with system frequency up to 1066MHz
  • 8 Internal banks for concurrent operation
  • 8n-bit prefetch architecture
  • Programmable CAS latency
  • Programmable additive latency - 0, CL-1, CL-2
  • Programmable CAS WRITE latency (CWL) based on tCK
  • Programmable burst length - 4 and 8
  • Sequential or interleave programmable burst sequence
  • BL switch on the fly
  • Auto Self Refresh (ASR)
  • Self refresh temperature (SRT)
  • Partial array self refresh
  • Asynchronous RESET pin
  • TDQS (termination data strobe) supported (x8 only)
  • OCD (Off-Chip Driver impedance adjustment)
  • Dynamic ODT (On-Die Termination)
  • RZQ/7, RZQ/6 (RZQ = 240R) Driver strength
  • Write levelling


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