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Ethernet Controller, 100 Mbps, IEEE 802.3, IEEE 802.3u, 3.135 V, 3.465 V, LQFP, 48 Pins

DM9161BEP - Ethernet Controller, 100 Mbps, IEEE 802.3, IEEE 802.3u, 3.135 V, 3.465 V, LQFP, 48 Pins

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DM9161BEP   Datasheet
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Product Overview

The DM9161BEP is a physical layer single-chip and Low Power Transceiver for 100BASE-TX and 10BASE-T operations. On the media side, it provides a direct interface either to Unshielded Twisted Pair Category 5 Cable (UTP5) for 100BASE-TX Fast Ethernet or UTP5/UTP3 Cable for 10BASE-T Ethernet. Through the Media Independent Interface (MII), the DM9161B connects to the Medium Access Control (MAC) layer, ensuring a high inter operability from different vendors. The DM9161B uses a low power and high performance advanced CMOS process. It contains the entire physical layer functions of 100BASE-TX as defined by IEEE802.3u, including the Physical Coding Sub layer (PCS), Physical Medium Attachment (PMA), Twisted Pair Physical Medium Dependent Sub layer (TP-PMD), 10BASE-TX Encoder/Decoder (ENC/DEC) and Twisted Pair Media Access Unit (TPMAU). The DM9161B provides a strong support for the auto-negotiation function, utilizing automatic media speed and protocol selection.
  • Fully comply with IEEE 802.3/IEEE 802.3u 10Base-T/100Base-TX, ANSI X3T12 TP-PMD 1995 standard
  • Support HP MDI/MDI-X auto crossover function (HP Auto-MDIX)
  • Support auto-negotiation function, compliant with IEEE 802.3u
  • Fully integrated physical layer transceiver on-chip filtering with direct interface
  • Selectable repeater or node mode
  • Selectable MII or RMII (reduced MII) mode for 100Base-TX and 10Base-TX
  • Selectable MII or GPSI (7-wired) mode for 10Base-T
  • Selectable full-duplex or half-duplex operation
  • MII management interface with mask able interrupt output capability
  • Provides loopback mode for easy system diagnostics
  • LED status outputs indicate link/activity, speed 10/100 and full-duplex/collision
  • Support dual-LED optional control
  • Single low power supply of 3.3V with an advanced CMOS technology
  • Compatible with 3.3 and 5.0V tolerant I/Os
  • Pin to pin compatible with DM9161A
  • DSP architecture PHY transceiver


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IEEE 802.3, IEEE 802.3u










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Technical Docs (1)

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