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Receiver Front End, Dual, 3.1 to 4.2 GHz, 4.75 to 5.25 V, -40 to 105 °C, LFCSP-EP-40


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Technical Datasheet:
ADRF5534BCPZN   Datasheet
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Product Overview

ADRF5534 is an integrated RF, front-end multichip module designed for time division duplex (TDD) applications. This device operates from 3.1GHz to 4.2GHz. It is configured with an LNA and a high-power, silicon, SPDT switch. In the receive operation at 3.6GHz, the LNA offers a low noise figure (NF) of 1.3dB and a high gain of 35.5dB with a third order input intercept point (IIP3) of -4dBm. In the transmit operation, the switch provides a low insertion loss of 0.8dB and handles a long-term evolution (LTE) average power of 37dBm for a full lifetime operation (8 dB peak to average ratio (PAR)) and 39dBm for a single event (10 sec) LNA protection operation. Application includes wireless infrastructure, TDD massive multiple input and multiple output (MIMO) and active antenna systems, TDD-based communication systems.
  • LNA and high-power silicon SPDT switch
  • On-chip bias and matching, single-supply operation
  • 35.5dB typical gain (ANT to RXOUT, VCC = 5V, T/R = 0V or 5V, TCASE = 25°C)
  • 1.5dB typical gain flatness (over any 400MHz bandwidth, VCC = 5V, T/R = 0V or 5V, TCASE = 25°C)
  • 1.3dB typical low noise figure (at 3.6GHz, VCC = 5 V, T/R = 0 V or 5 V, TCASE = 25°C)
  • 0.8dB typical insertion loss (ANT to TERM, VCC = 5V, T/R = 0V or 5V, TCASE = 25°C)
  • 25dB typical output return loss (ANT to TERM, VCC = 5V, T/R = 0V or 5V, TCASE = 25°C)
  • 650ns typical settling time (ANT to TERM, 50% of T/R to 0.3dB of RF output)
  • Supply voltage range from 4.7 to 5.25V (ANT to TERM, VCC = 5V, T/R = 0V or 5V, TCASE = 25°C)
  • 24 lead LFCSP package, operating temperature range from -40°C to +105°C

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Technical Documents (1)

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